Semiconductor devices such as microprocessors, microcontrollers and communication chips are used extensively in electronic devices including computers. Generally semiconductor devices include a plurality of integrated circuits (ICs). ICs can contain millions of transistors and other circuit elements fabricated on a single semiconductor chip. For device functionality, numerous circuit lines will typically be routed to connect the circuit elements distributed on the surface of the semiconductor device. Efficient routing of the electrical signals can become more difficult as the number and complexity of the ICs increases. Multilevel or multilayered interconnect circuit lines are used to provide efficacy in providing high-speed signal routing patterns between a large number of transistors on the semiconductor chip.
Back-end-of-the line (BEOL) wiring interconnects are prepared on IC chips by a complex combination of lithography, etching, ashing, hard mask and possibly etchstop deposition, liner and metal deposition, chemical mechanical polishing, cleaning, etc. This integration is extraordinarily demanding and expensive. For utilization of copper metallurgy, lithographic images over a planar dielectric are developed and transferred by etching. After metal overdeposition, the excess metal is removed by chemical mechanical polishing (CMP). This procedure is followed for the formation of all of the metal lines in each dielectric layer and the vias which connect the various wiring layers. If the lines and vias are generated in separate processes, this is called a single damascene (SD) processes. If both the line and the vias are processed simultaneously, the process is called dual damascene (DD).
With the ever-growing demand for higher performance at lower cost, the feature dimensions of integrated circuits continue to shrink. As a consequence, there is an increase in the interconnect (RC) delay and signal degradation at the BEOL wiring of semiconductor chips.
In order to reduce the capacitance, conventional insulating materials such as SiO2 are being replaced with dielectric materials that have a lower dielectric constant (low-k). Since SiO2 has a dielectric constant of ˜4.0, low-k materials should have k values substantially less than this. The lower dielectric constant materials improve chip performance by mitigating signal delay and decreasing power consumption. The materials currently used in the 90 nm technology node are organosilicates deposited either by spin-on or CVD techniques These materials have a dielectric constant of <3.0. The dielectric constant of the insulating materials must be further reduced for the 65 nm technology node and further reductions are necessary for future generations of products. Due to the low dielectric constant of air (k=1.01), the decrease in dielectric constant to values below 2.2 can be accomplished by the introduction of porosity in the dielectric materials during the manufacturing process. For this, pore generators (porogens) are often introduced into the dielectric formulation.
Unfortunately, the introduction of porosity into an insulating dielectric layer normally results in a degradation of thermal, electrical and, in particular, mechanical properties. All of this is endured to achieve a decrease in the dielectric constant of the dielectric material. The relentless push to lower dielectric constant makes the eventual use of porous materials inevitable. Porous materials with dielectric constants down to k=2.0 and lower have been described. The porous materials can be organic polymers or inorganic-organic hybrid materials (e.g., organosilicates), although the latter are much more numerous.
The minimum achievable dielectric constant for an insulating medium would be that of air (k=1.01) or other common gases. The replacement therefore of solid layer of insulating material between metal insulating lines with air gaps would deliver the maximum decrease in the dielectric constant. However, the incorporation of air gaps leads to numerous mechanical and thermal issues. The low thermal conductivity of gases makes it more difficult to dissipate power, thereby exacerbating chip heating problems. The second issue is loss of mechanical support for the wiring, capping layers and other necessary structures in the BEOL portion of the chip. In spite of the formal technological difficulties, a number of integration schemes employing air bridges are known.
Colbum US 2005/0079719A1 discloses a damascene process which uses a self assembled, block copolymer layer which is processed to form nano holes in the layer. The layer is then used as a template to transfer a pattern of circular holes into a dielectric layer to form columns of air in the dielectric layer. Unfortunately, with this procedure, there is a limited amount of air that can be introduced into the dielectric layer due to the geometric design of the columns of air in Colburn's template. Further, because Colburn's template comprises an organic polymer, etch selectivity can be limited due to the limited thickness of a film that can be obtained with self assembled polymer films. There still is a need for improved dielectric materials having low k values and suitable electrical and mechanical properties.